Semiconductor memory device having multi-layered storage node contact plug and method for fabricating the same

ABSTRACT

A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory deviceand a method for fabricating the same, and more particularly, to asemiconductor memory device having a storage node contact plug and amethod for fabricating the same.

[0003] 2. Description of the Related Art

[0004] In semiconductor memory devices such as DRAM (Dynamic RandomAccess Memory) devices, a variety of contact holes are employed,including for example, a pad contact hole, a bit line contact hole, astorage node contact hole, a metal contact hole and a via contact hole.Among these contact holes, the storage node contact hole is very small,because it must be formed in a narrow region between the bit lines, anddifficult to form, because it is created by deeply etching an interlayerdielectric layer. Moreover, to form the storage node contact hole in thenarrow region between the bit lines, high level and precise alignmentskills are required in the photolithography process. It is verydifficult to reproducibly form a storage node contact hole since analignment margin of 30 nm or less is required for a design rule of 0.15μm or less.

[0005] Accordingly, a method for forming a storage node contact holeusing a self-align contact etching process has been proposed. In theself-align contact etching process, after covering a bit line with asilicon nitride layer, the storage node contact hole is formed byetching an interlayer dielectric layer to be aligned at the siliconnitride layer, by taking advantage of the etching selectivity of theinterlayer dielectric layer with respect to the silicon nitride layer.Next, a storage node contact plug material layer is formed in thestorage node contact hole and then the storage node contact plugmaterial layer is etched back, thereby forming a storage node contactplug. Thereafter, a storage node of a capacitor is formed on the storagenode contact plug.

[0006] In highly integrated semiconductor memory devices, since thestorage node is formed of a metal layer, the storage node plug materiallayer is also formed of a metal layer, such as a tungsten layer or atitanium nitride layer, in the self-align contact etching process.

[0007] However, when tungsten is used as the storage node contact plugmaterial, the etching selection ratio (etching selectivity) of thestorage node contact plug material layer (i.e., tungsten) with respectto the silicon nitride layer covering the bit line is poor. As a result,the storage node contact plug material layer made of tungsten isdamaged, rather than being selectively etched. Such damage may cause ashort circuit between the storage node contact plug and the bit line.Moreover, as the design rule decreases, the silicon nitride layerbecomes thinner. Thus, if the silicon nitride layer is completelydestroyed, margins for the self-align contact etching process aresignificantly decreased.

[0008] If the storage node contact plug material layer is formed of atitanium nitride layer, cracks may occur due to a large amount of stressat the titanium nitride layer when depositing the titanium nitride layerto have a thickness greater than a certain value. Moreover, the cracksmay propagate to the interlayer dielectric layer, thereby causingserious problems.

SUMMARY OF THE INVENTION

[0009] To solve the above problems, it is a first object of the presentinvention to provide a semiconductor memory device which is capable ofsolving problems occurring when forming a storage node contact plugmaterial layer comprising tungsten or titanium nitride.

[0010] It is a second object of the present invention to provide amethod for fabricating the semiconductor memory device.

[0011] Accordingly, to achieve the first object, there is provided asemiconductor memory device. The semiconductor memory device includes abit line stack, and a storage node contact hole aligned at bit linespacers formed at both side walls of the bit line stack and exposing apad. In the storage node contact hole, a multi-layered storage nodecontact plug is formed by sequentially forming a first storage nodecontact plug and a second storage node contact plug.

[0012] Preferably, the first storage node contact plug is formed of atitanium nitride layer and the second storage node contact plug isformed of a polysilicon layer. An ohmic layer may be further formed onthe pad and under the first storage node contact plug. A barrier metallayer, which acts as a third storage node contact plug, may be furtherformed on the second storage node contact plug.

[0013] According to another aspect of the present invention, asemiconductor memory device includes an interlayer dielectric layerformed to insulate a pad on a semiconductor substrate, and a bit linestack formed on the interlayer dielectric layer. The semiconductormemory device includes a pair of bit line spacers, which are formed atboth side walls of the bit line stack, and has a storage node contacthole exposing the surface of the pad formed therebetween. In the storagenode contact hole, a multi-layered storage node contact plug is formed,in which a first storage node contact plug and a second storage nodecontact plug are sequentially formed.

[0014] Preferably, the first storage node contact plug is formed of atitanium nitride layer and the second storage node contact plug isformed of a polysilicon layer. Preferably, the bit line stack consistsof a bit line barrier metal layer, a bit line conductive layer, and abit line cap layer which are sequentially deposited. Preferably, the bitline barrier metal layer is formed of a titanium nitride layer, the bitline conductive layer is formed of a tungsten layer, and the bit linecap layer is formed of a silicon nitride layer. A barrier metal layer,which acts as a third storage node contact plug, may be further formedon the second storage node contact plug.

[0015] To achieve the second object of the present invention, there isprovided a method for fabricating a semiconductor memory deviceincluding forming a bit line stack on a semiconductor substrate, onwhich an interlayer dielectric layer for insulating a pad is formed. Apair of bit line spacers are formed at both side walls of the bit linestack. A storage node contact hole is formed to be aligned at the bitline spacers and expose the pad in the interlayer dielectric layer byusing a self align contact etching method. A multi-layered storage nodecontact plug, which consists of a first storage node contact plug and asecond node contact plug, is formed in the storage node contact hole.

[0016] Preferably, the first storage node contact plug is formed of atitanium nitride layer and the second storage node contact plug isformed of a polysilicon layer. A barrier metal layer, which acts as athird storage node contact plug, may be further formed on the secondstorage node contact plug.

[0017] The multi-layered storage node contact plug is formed by thefollowing steps. A first storage node contact plug material layer isformed on the entire surface of the semiconductor substrate after thestorage node contact hole is formed. A second storage node contact plugmaterial layer is formed on the first storage node contact plug materiallayer to sufficiently fill the storage node contact hole. A secondstorage node contact plug is formed in the storage node contact hole byetching back the second storage node contact plug material layer. Abarrier metal material layer is formed on the entire surface of thesemiconductor substrate on which the second storage node contact plug isformed. The first storage node contact plug material layer and thebarrier metal material layer on the bit line stack are then etched tocomplete the multi-layered storage node.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above objects and advantages of the present invention willbecome more apparent by describing in detail a preferred embodimentthereof with reference to the attached drawings in which:

[0019]FIG. 1 is a cross-sectional view illustrating a semiconductormemory device having a multi-layered storage node contact plug accordingto the present invention; and

[0020]FIGS. 2 through 6 are cross-sectional views illustrating a methodfor fabricating a semiconductor memory device having a multi-layeredstorage node contact plug as in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0021] The present invention will now be described more fully withreference to the accompanying drawings, in which a preferred embodimentof the invention is shown. This invention may, however, be embodied inmany different forms and should not be construed as being limited to theembodiment set forth herein. Rather, this embodiment is provided so thatthis disclosure will be thorough and complete, and will fully convey theconcept of the invention to those skilled in the art. In the drawings,the thickness of layers and regions are exaggerated for clarity. It willalso be understood that when a layer is referred to as being “on”another layer or substrate, it can be directly on the other layer orsubstrate, or intervening layers may also be present.

[0022]FIG. 1 shows a semiconductor memory device having a multi-layeredstorage node contact plug according to the present invention.Specifically, a pad 13, and an interlayer dielectric layer 15 forinsulating the pad 13, are formed on a semiconductor substrate 11 suchas a silicon substrate. The pad 13 is formed of a polysilicon layer andthe interlayer dielectric layer 15 is formed of a silicon oxide layer.

[0023] A bit line stack 23 is formed on the interlayer dielectric layer15. The bit line stack includes a bit line barrier metal layer 17, a bitline conductive layer 19, and a bit line cap layer 21. The bit linebarrier metal layer 17, the bit line conductive layer 19 and the bitline cap layer 21 are formed of a titanium nitride layer, a tungstenlayer and a silicon nitride layer, respectively.

[0024] A pair of bit line spacers 25 are formed at both side walls ofthe bit line stack 23. The bit line spacers 25 are formed of a siliconnitride layer. A storage node contact hole 26 is formed within theinterlayer dielectric layer 15 so as to be aligned between the bit linespacers 25 and expose the pad.

[0025] An ohmic layer 27 a is formed in the storage node contact hole26. The ohmic layer 27 a is formed of titanium (Ti), cobalt (Co),molybdenum (Mo) or tungsten (W). A multi-layered storage node contactplug, consisting of a first storage node contact plug 29 a and a secondstorage node contact plug 31 a, is formed on the ohmic layer 27 a withinthe storage node contact hole 26. The second storage node contact plug31 a is formed to be thicker than the first storage node contact plug 29a. The first storage node contact plug 29 a is formed of a titaniumnitride layer and the second storage node contact plug 31 a is formed ofan impurity-doped polysilicon layer.

[0026] The first storage node contact plug 29 a formed of titaniumnitride acts as a barrier metal layer. The second storage node contactplug 31 a formed of polysilicon can be etched more easily than aconventional storage node contact plug formed of tungsten. In addition,the second storage node contact plug 31 has a superior etching selectionrate, or etching selectivity, with respect to a silicon nitride layer ora titanium nitride layer. A barrier metal layer 33 a for forming astorage node of a capacitor is formed on the second storage node contactplug 29 a. The barrier metal layer 33 a is formed of a titanium nitridelayer (TiN) or a tantalum nitride layer (TaN). The barrier metal layer33 a used in the present embodiment can be used as a third storage nodecontact plug.

[0027]FIGS. 2 through 6 are cross-sectional views illustrating a methodfor fabricating a semiconductor memory device having a multi-layeredstorage node contact plug according to the present invention.

[0028] Referring to FIG. 2, a bit line stack 23 is formed on asemiconductor substrate 11, such as a silicon substrate, on which a pad13 and an interlayer dielectric layer 15 for insulating the pad 13 havebeen formed. The pad 13 is formed of a polysilicon layer and theinterlayer dielectric layer 15 is formed of a silicon oxide layer. Thebit line stack 23 is formed by sequentially depositing a bit linebarrier metal layer 17, a bit line conductive layer 19, and a bit linecap layer 21. The bit line barrier metal layer 17, the bit lineconductive layer 19, and the bit line cap layer 21 are formed of atitanium nitride layer, a tungsten layer and a silicon nitride layer,respectively.

[0029] Next, a pair of spacers 25 are formed at both side walls of thebit line stack 23. The bit line spacers 25 are formed of a siliconnitride layer. Then, a storage node contact hole 26 is formed in theinterlayer dielectric layer 15 so as to be aligned at the bit linespacers 25 and expose the pad. Here, a self-align contact etching methodis needed because the storage node contact hole 26 is formed to beself-aligned at the bit line spacers 25 by etching the interlayerdielectric layer 15.

[0030] Referring to FIG. 3, an ohmic material layer 27 is formed on theentire surface of the semiconductor substrate 11 where the storage nodecontact hole 26 is formed. The ohmic material layer 27 is formed oftitanium (Ti), cobalt (Co), molybdenum (Mo) or tungsten (W) so as tohave a thickness between about 30 Å to about 100 Å. A first storage nodecontact plug material layer 29 is formed on the ohmic material layer 27.The first storage node contact plug material layer 29 is formed of atitanium nitride layer so as to have a thickness between about 200 Å toabout 700 Å. The first storage node contact plug material layer 29 actsas a barrier metal layer. Note that the ohmic material layer 27 andfirst storage node contact plug material layer 29 are formed on thesidewalls of, and partially fill, the storage node contact plug 26.

[0031] Referring to FIG. 4, a second storage node contact plug materiallayer 31 is formed on the entire surface of the semiconductor substrate11 on which the first storage node contact plug material layer 29 isformed, so as to completely fill the storage node contact hole 26. Thesecond storage node contact plug material layer 31 is formed to bethicker than the first storage node contact plug material layer 29. Thesecond storage node contact plug material layer 31 is formed of animpurity-doped polysilicon layer, which can fill the storage nodecontact hole 26 more completely and can be etched more easily than thetungsten layer used in the prior art.

[0032] Referring to FIG. 5, the second storage node contact plugmaterial layer 31 is etched back by a conventional etching method,thereby forming a second storage node contact plug 31 a within thestorage node contact hole 26. The second storage node contact plug 31 acan be formed easily by taking advantage of a superior etchingselectivity between the second storage node contact plug material layer31 (formed of polysilicon) and the first storage node contact plug 29(formed of a titanium nitride). In other words, the polysilicon layerforming the second storage node contact plug material layer 31 has ahigh etching rate with respect to the titanium nitride layer forming thefirst storage node contact plug 29 and thus, only the polysilicon layeris etched.

[0033] Referring to FIG. 6, a barrier metal material layer 33 is formedon the entire surface of the semiconductor substrate 11 on which thesecond storage node contact plug 31 a is formed. The barrier metalmaterial layer 33 is formed of a titanium nitride layer or a tantalumnitride layer to have a thickness between about 700 Å to about 1000 Å.The barrier metal material layer 33 is thinly deposited to have such athickness, thereby preventing cracks and making it easy to etch thebarrier metal material layer.

[0034] Next, as described in FIG. 1, the ohmic material layer 27, thefirst storage node contact plug material layer 29, and the barrier metalmaterial layer 33 are etched back to the height of the bit line caplayer 21, thereby creating ohmic layer 27 a, first storage node contactplug 29 a, and barrier metal layer 33 a.

[0035] As a result, the ohmic layer 27 a is formed in the storage nodecontact hole 26, and a multi-layered storage node contact plug,comprising the first storage node contact plug 29 a and the secondstorage node contact plug 31 a, is formed on the ohmic layer 27 a. Thebarrier metal layer 33 a is formed on the second storage node contactplug 31 a. The barrier metal layer 33 a used in the present inventioncan be used as a third storage node contact plug. If the first storagenode contact plug material layer 31 is etched more deeply, the barriermetal layer 33 a becomes the third storage node contact plug.

[0036] As described above, according to the present invention, thestorage node contact plug buried in a storage node contact hole consistsof a titanium nitride layer and a polysilicon layer, by which marginsfor a process can be improved by taking advantage of a high etchingselection ratio of the titanium nitride layer or the polysilicon layerwith respect to a tungsten layer used in the prior art. Moreover, theoccurrence of cracks can be prevented in a process for forming thestorage node contact plug of a titanium nitride layer.

[0037] While this invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made to the described embodiments without departing from the spiritand scope of the invention as defined by the appended claims.

What is claimed is:
 1. A semiconductor memory device, having a storagenode contact hole aligned at bit line spacers formed at both side wallsof a bit line stack and exposing a pad, the device comprising amulti-layered storage node contact plug formed in the storage nodecontact hole, the mulit-layered storage node contact plug having a firststorage node contact plug and a second storage node contact plug formedon the first storage node contact plug.
 2. The semiconductor memorydevice of claim 1, wherein the first storage node contact plug is formedof a titanium nitride layer and the second storage node contact plug isformed of a polysilicon layer.
 3. The semiconductor memory device ofclaim 1, further comprising an ohmic layer formed on the pad and underthe first storage node contact plug.
 4. The semiconductor memory deviceof claim 3, wherein the ohmic layer is formed of one of the groupconsisting of titanium (Ti), cobalt (Co), molybdenum (Mo) and tungsten(W).
 5. The semiconductor memory device of claim 1, further comprising abarrier metal layer formed on the second storage node contact plug,wherein the barrier metal layer functions as a third storage nodecontact plug.
 6. The semiconductor memory device of claim 5, wherein thebarrier metal layer is formed of one of a titanium nitride layer and atantalum nitride layer.
 7. The semiconductor memory device of claim 1,wherein the pad is formed of a polysilicon layer.
 8. The semiconductormemory device of claim 1, wherein the second storage node contact plughas a thickness greater than a thickness of the first storage nodecontact plug.
 9. A semiconductor memory device, comprising: a pad formedon a semiconductor substrate; an interlayer dielectric layer formed onthe pad and substrate to insulate the pad; a bit line stack formed onthe interlayer dielectric layer; a pair of bit line spacers formed atboth side walls of the bit line stack; a storage node contact hole,formed within the interlayer dielectric layer, exposing the pad andaligned between the bit line spacers; and a multi-layered storage nodecontact plug formed within the storage node contact hole, including afirst storage node contact plug and a second storage node contact plugformed on the first storage node contact plug.
 10. The semiconductormemory device of claim 9, wherein the first storage node contact plug isformed of a titanium nitride layer and the second storage node contactplug is formed of a polysilicon layer.
 11. The semiconductor memorydevice of claim 9, wherein the bit line stack comprises a bit linebarrier metal layer, a bit line conductive layer, and a bit line caplayer which are sequentialy deposited.
 12. The semiconductor memorydevice of claim 11, wherein the bit line barrier metal layer is formedof a titanium nitride layer, the bit line conductive layer is formed ofa tungsten layer, and the bit line cap layer is formed of a siliconnitride layer.
 13. The semiconductor memory device of claim 9, furthercomprising a barrier metal layer formed on the second storage nodecontact plug.
 14. A method for fabricating a semiconductor memory devicecomprising: forming a pad on a semiconductor substrate; forming aninterlayer dielectric layer on the pad and semiconductor substrate forinsulating the pad; forming a bit line stack on the interlayerdielectric layer; forming a pair of bit line spacers at both side wallsof the bit line stack; forming a storage node contact hole in theinterlayer dielectric layer using a self align contact etching method,the storage node contact hole being aligned at the bit line spacers andexposing the pad; and forming a multi-layered storage node contact plugin the storage node contact hole, by sequentially forming a firststorage node contact plug and a second node contact plug in the storagenode contact hole.
 15. The method for fabricating a semiconductor memorydevice of claim 14, wherein the first storage node contact plug isformed of a titanium nitride layer and the second storage node contactplug is formed of a polysilicon layer.
 16. The method for fabricating asemiconductor memory device of claim 14, further comprising forming abarrier metal layer on the second storage node contact plug, the barriermetal layer functioning as a third storage node contact plug.
 17. Themethod for fabricating a semiconductor memory device of claim 16,wherein the barrier metal layer is formed of one of a titanium nitridelayer and a tantalum nitride layer.
 18. The method for fabricating asemiconductor memory device of claim 16, wherein the forming of themulti-layered storage node contact plug comprises: forming a firststorage node contact plug material layer on an entire surface of thesemiconductor substrate after the storage node contact hole is formed,thereby partially filling the storage node contact hole; forming asecond storage node contact plug material layer on the first storagenode contact plug material layer to sufficiently fill the storage nodecontact hole; forming a second storage node contact plug in the storagenode contact hole by etching back the second storage node contact plugmaterial layer; forming a barrier metal material layer on the entiresurface of the semiconductor substrate on which the second storage nodecontact plug is formed; and etching the first storage node contact plugmaterial layer and the barrier metal material layer on the bit linestack.
 19. The method for fabricating a semiconductor memory device ofclaim 14, further comprising forming an ohmic layer on the pad and underthe first storage node contact plug.
 20. The method for fabricating asemiconductor memory device of claim 19, wherein the ohmic layer isformed of one selected from the group consisting of titanium (Ti),cobalt (Co), molybdenum (Mo) and tungsten (W).